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lnk403-409/413-419 linkswitch-ph led driver ic family www.powerint.com august 2011 single-stage pfc, primary-side constant current control and triac dimming/non-dimming options ? output power table 1,2 product 5 r v = 2 m w r v = 4 m w 85-132 vac 85-308 vac minimum output power 3 maximum output power 4 minimum output power 3 maximum output power 4 lnk403/413e/l 2.5 w 4.5 w 6.5 w 12 w lnk404/414e/l 2.5 w 5.5 w 6.5 w 15 w lnk405/415e/l 3.8 w 7.0 w 8.5 w 18 w lnk406/416e/l 4.5 w 8.0 w 10 w 22 w lnk407/417e/l 5.5 w 10 w 12 w 25 w lnk408/418e/l 6.8 w 13.5 w 16 w 35 w lnk409/419e/l 8.0 w 20 w 18 w 50 w table 1. output power table. notes : 1. continuous power in an open frame with adequate heat sinking at device local ambient of 70 c. 2. power level calculated on typical led string voltage with effciency > 80%. 3. minimum output power with c bp = 10 m f. 4. maximum output power with c bp = 100 m f. lnk4x3eg c bp = 10 m f. 5. package: esip-7c, esip-7f . product highlights dramatically simplifes off-line led drivers ? single-stage combination of power factor correction and accurate constant-current (cc) output ? enables very long lifetime designs (no electrolytic capacitors) ? eliminates optocoupler and all secondary current control circuitry ? eliminates control loop compensation circuitry ? simple primary-side pwm dimming interface ? universal input voltage range ? lnk403-409 optimized for ficker-free triac dimming ecosmart ? C energy effcient ? single-stage pfc combined with output cc control ? greatly increases effciency, >90% achievable ? reduces component count ? no current sense resistors ? low standby power remote on/off feature (<50 mw at 230 vac) accurate and consistent performance ? compensates for transformer inductance variations ? compensates for line input voltage variation ? frequency jittering greatly reduces emi flter size and cost advanced protection and safety features ? auto-restart for short-circuit protection ? open circuit fault detection mode ? automatic thermal shutdown restart with hysteresis ? meets high voltage creepage requirement between drain and all other signal pins both on pcb and at package green package ? halogen free and rohs compliant package applications ? off-line led driver description the linkswitch-ph dramatically simplifes implementation of led drivers requiring long lifetime, high effciency, pf > 0.9, and triac dimming capability (lnk403-409). the single-stage combined power factor and constant-current controller eliminates a switching stage and the electrolytic bulk capacitor. the advanced primary- side control used by the linkswitch-ph device provides accurate constant current control while eliminating the need for an optocoupler and current sensing circuits. linkswitch-ph incorporates a 725 v power fet, a continuous- mode pwm controller, a high voltage switched current source for self biasing, frequency jittering, protection circuitry including cycle-by-cycle current limit and hysteretic thermal shutdown. figure 2. package options. esip-7f (l package) esip-7c (e package) figure 1. typical application schematic. pi-6543-082211 linkswitch-ph ac in d s bp v fb r control r v
rev. d 08/11 2 lnk403-409/413-419 www.powerint.com figure 4. pin confguration. pin functional description drain (d) pin: this pin is the power fet drain connection. it also provides internal operating current for both start-up and steady-state operation. source (s) pin: this pin is the power fet source connection. it is also the ground reference for the bypass, feedback, reference and voltage monitor pins. bypass (bp) pin: this is the connection point for an external bypass capacitor for the internally generated 5.9 v supply. this pin also provides output power selection through choice of the bypass pin capacitor value. feedback (fb) pin: the feedback pin is used for output voltage feedback. the current into the feedback pin is directly proportional to the output voltage. the feedback pin also includes circuitry to protect against open load and overload output conditions. reference (r) pin: this pin is connected to an external precision resistor and is used to confgure for dimming (lnk403-409) and non-triac dimming (lnk413-419) modes of operation. voltage monitor (v) pin: this pin interfaces with an external input line peak detector, consisting of a rectifer, flter capacitor and resistors. the applied current is used to control stop logic for line under- voltage (uv), overvoltage (ov), provide feed-forward to control the output current and the remote on/off function. pi-5431-102610 i lim drain (d) source (s) bypass (bp) voltage monitor (v) feedback (fb) reference (r) i lim v sense m i i s 5.9 v 5.0 v bypass pin undervoltage fault present gate driver sensefet ocp current limit comparator 1 v 6.4 v fb off fb off i fb i v dc max dc max comparator 5.9 v regulator soft-start timer jitter clock oscillator auto-restart counter bypass capacitor select feedback sense pfc/cc control line sense hysteretic thermal shutdown + - + - + - 3-v t v bg uv/ov reference block leb m i v bg stop logic pi-5432-082411 exposed pad (backside) internally connected to source pin (see esip-7c package drawing) 1 r 2 v 3 fb 4 bp 5 s 7 d e package (esip-7c) (top view) lead bend outward from drawing (refer to esip-7f package outline drawing) exposed pad (backside) internally connected to source pin 7 d 5 s 4 bp 3 fb 2 v 1 r l package (esip-7f) figure 3. functional block diagram.
rev. d 08/11 3 lnk403-409/413-419 www.powerint.com functional description a linkswitch-ph device monolithically integrates a controller and high-voltage power fet into one package. the controller implements both high power factor and a constant current output in a single stage. the linkswitch-ph controller consists of an oscillator, feedback (sense and logic) circuit, 5.9 v regulator, hysteretic over-temperature protection, frequency jittering, cycle-by-cycle current limit, auto-restart, inductance correction, power factor and constant current control. feedback pin current control characteristics the fgure shown below illustrates the operating boundaries of the feedback pin current. above i fb(skip) switching is disabled and below i fb(ar) the device enters into auto-restart. figure 5. feedback pin current characteristic. the feedback pin current is also used to clamp the maximum duty cycle to limit the available output power for overload and open-loop conditions. this duty cycle reduction characteristic also promotes a monotonic output current start-up characteristic to prevent over-shoot. reference pin the reference pin is tied to ground (source) via an external resistor. the value selected sets the internal references, determining the operating mode for dimming (lnk403-409) and non-dimming (lnk413-419) operation and the line undervoltage and overvoltage thresholds of the voltage monitor pin. for non-dimming or pwm dimming applications with lnk413-419, the external resistor should be a 24.9 k w 1%, for high-line and universal input voltage designs, and 49.9 k w 1% for low-line input voltage designs. for phase angle ac dimming with lnk403-409, the external resistor should be a 49.9 k w 1%. one percent resistors are recommended as the resistor tolerance directly affects the output tolerance. other resistor values should not be used. bypass pin capacitor power gain selection linkswitch-ph devices have the capability to tailor the internal gain to either full or a reduced output power setting. this allows selection of a larger device to minimize dissipation for both thermal and effciency reasons. the power gain is selected with the value of the bypass pin capacitor. the full power setting is selected with a 100 m f capacitor and the reduced power setting (for higher effciency) is selected with a 10 m f capacitor. the bypass pin capacitor sets both the internal power gain as well as the over-current protection (ocp) threshold. unlike the larger devices, the lnk4x3 power gain is not programmable. use a 10 m f capacitor for the lnk4x3. switching frequency the switching frequency is 66 khz. to further reduce the emi level, the switching frequency is jittered (frequency modulated) by approximately 1 khz. soft-start the controller includes a soft-start timing feature which inhibits the auto-restart protection feature for the soft-start period (t soft ) to distinguish start-up into a fault (short-circuit) from a large output capacitor. at start-up the linkswitch-ph clamps the maximum duty cycle to reduce the output power. the total soft-start period is t soft . remote on/off and ecosmart the voltage monitor pin has a 1 v threshold comparator connected at its input. this voltage threshold is used for remote on/off control. when a signal is received at the voltage monitor pin to disable the output (voltage monitor pin tied to ground through an optocoupler photo- transistor) the linkswitch-ph will complete its current switching cycle before the internal power fet is forced off. the remote on/off feature can also be used as an eco-mode or power switch to turn off the linkswitch-ph and keep it in a very low power consumption state for indefnite long periods. when the linkswitch-ph is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the bypass pin reaches 5.9 v. in the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the bypass pin. this reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. i fb(ar) i fb(dcmaxr) dc10 dc max i fb(skip) i fb pi-5433-060410 skip-cycle cc control region soft-start and cc fold-back region auto-restart maximum duty cycle
rev. d 08/11 4 lnk403-409/413-419 www.powerint.com figure 6. remote on/off voltage monitor pin control 5.9 v regulator/shunt voltage clamp the internal 5.9 v regulator charges the bypass capacitor connected to the bypass pin to 5.9 v by drawing a current from the voltage on the drain pin whenever the power fet is off. the bypass pin is the internal supply voltage node. when the power fet is on, the device operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows linkswitch-ph to operate continuously from current it takes from the drain pin. a bypass capacitor value of 10 or 100 m f is suffcient for both high frequency decoupling and energy storage. in addition, there is a 6.4 v shunt regulator clamping the bypass pin at 6.4 v when current is provided to the bypass pin through an external resistor. this facilitates powering of linkswitch-ph externally through a bias winding to increase operating effciency. it is recommended that the bypass pin is supplied current from the bias winding for normal operation. auto-restart in the event of an open-loop fault (open feedback pin resistor or broken path to feedback winding), output short-circuits or an overload condition the controller enters into the auto-restart mode. the controller annunciates both short-circuit and open-loop conditions once the feedback pin current falls below the i fb(ar) threshold after the soft-start period. to minimize the power dissipation under this fault condition the shutdown/auto-restart circuit turns the power supply on (same as the soft-start period) and off at an auto-restart duty cycle of typically dc ar for as long as the fault condition persists. if the fault is removed during the auto-restart off-time, the power supply will remain in auto-restart until the full off-time count is completed. special consideration must be made to appropriately size the output capacitor to ensure that after the soft-start period (t soft ) the feedback pin current is above the i fb(ar) threshold to ensure successful power-supply start-up. after the soft-start time period, auto-restart is activated only when the feedback pin current falls below i fb(ar) . over-current protection the current limit circuit senses the current in the power fet. when this current exceeds the internal threshold (i limit ), the power fet is turned off for the remainder of that cycle. a leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power fet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and rectifer reverse recovery will not cause premature termination of the power fet conduction. line under/overvoltage protection this device includes both line under- and overvoltage detection to limit the minimum start-up and maximum operating voltage detected through the voltage monitor pin. an external peak detector consisting of a diode and capacitor are required to provide input line peak voltage to the voltage monitor pin through a resistor. at power up, i uv+ keeps the linkswitch-ph off until the input line voltage reaches the undervoltage threshold. at power down, i uv- prevents restart attempts after the output goes out of regulation. the same resistor used for uv also sets line overvoltage (ov) shutdown threshold which, once exceeded, forces the linkswitch-ph to stop switching (after completion of the current switching cycle). once the line voltage returns to normal, the device resumes normal operation. a small amount of hysteresis is provided on the ov threshold to prevent noise triggering. when the power fet is off, the rectifed dc high voltage surge capability is increased to the voltage rating of the power fet (725 v), due to the absence of the refected voltage and leakage spikes on the drain. hysteretic thermal shutdown the thermal shutdown circuitry senses the controller die temperature. the threshold is set at 142 c typical with a 75 c hysteresis. when the die temperature rises above this threshold (142 c) the power fet is disabled and remains disabled until the die temperature falls by 75 c, at which point the power fet is re-enabled. safe operating area (soa) protection the device also features a safe operating area (soa) protection mode which disables fet switching for 40 cycles in the event the peak switch current reaches the ilimit threshold and the switch on-time is less than t on(soa) . this protection mode protects the device under short-circuited led conditions and at start-up during the soft-start period when auto-restart protection is inhibited. the soa protection mode remains active in normal operation. pi-5435-052510 d s bp v r fb control
rev. d 08/11 5 lnk403-409/413-419 www.powerint.com application example 14 w triac dimmable high power factor led driver design example the circuit schematic in figure 7 shows a triac dimmable high power-factor led driver based on lnk406eg from the linkswitch-ph family of devices. it was optimized to drive an led string at a voltage of 28 v with a constant current of 0.5 a (5%) ideal for par lamp retro-ft applications. the design operates over a universal input voltage range of 90 vac to 265 vac but provides the specifed output current tolerance over a line voltage range of 90 vac to 132 vac (this is confgurable for high-line only applications by simple component value changes). the key goals of this design were compatibility with standard leading edge triac ac dimmers, very wide dimming range (1000:1, 500 ma:0.5 ma), high effciency (>85%) and high power factor (>0.9). the design is fully protected from faults such as no-load, overload and output short-circuit conditions and over temperature. circuit description the linkswitch-ph device (u1) integrates the power fet, controller and start-up functions into a single package reducing the component count versus typical implementations. confgured as part of an isolated continuous conduction mode fyback converter, u1 provides high power factor via its internal control algorithm together with the small input capacitance of the design. continuous conduction mode operation results in reduced primary peak and rms current. this both reduces emi noise, allowing simpler, smaller emi fltering components and improves effciency. output current regulation is maintained without the need for secondary side sensing which eliminates current sense resistors and improves effciency. input stage fuse f1 provides protection from component failures while rv1 provides a clamp during differential line surges, keeping the peak drain voltage of u1 below the 725 v rating of the internal power fet. bridge rectifer br1 rectifes the ac line voltage. emi fltering is provided by l1-l3, c1, r16 and r17 together with the safety rated y class capacitor (c7) that bridges the safety isolation barrier between primary and secondary. resistor r16 and r17 act to damp any resonances formed between l1, l2, c1 and the ac line impedance. a small bulk capacitor (c2) is required to provide a low impedance source for the primary switching current. the maximum value of c1 and c2 is limited in order to maintain a power factor of greater than 0.9. linkswitch-ph primary to provide peak line voltage information to u1 the incoming rectifed ac peak charges c3 via d2. this is then fed into the voltage monitor pin of u1 as a current via r2 and r3. this sensed current is also used by the device to set the line input overvoltage and undervoltage protection thresholds. resistor r1 provides a discharge path for c3 with a time constant much longer than that of the rectifed ac to prevent generation of line frequency ripple. the voltage monitor pin current and the feedback pin current are used internally to control the average output led current. for triac phase-dimming applications a 49.9 k w resistor (r4) is used on the reference pin and 4 m w (r2+r3) on the voltage monitor pin to provide a linear relationship between input voltage and the output current and maximizing the dimming range. resistor r4 also sets the internal line input undervoltage and overvoltage protection thresholds. r11 2.4 m r9 750 k 1% r10 750 k 1% pi-5997-061510 d s bp v r fb control fl1 t1 rm8 11 1 fl2 3 2 r2 2 m 1% r1 240 k 1/2 w r16 1 k l1 1000 h l3 1000 h l2 1000 h r17 1 k r3 2 m 1% r4 49.9 k 1% r6 162 k 1% r15 20 k 28 v, 500 ma 90 - 265 vac rtn l n r7 10 k r8 150 r5 3 k r19 1 k d2 dl4007 d3 uf4007 d5 1n4148 vr3 zmm5259b-7 39 v q3 mmbt3904 d7 bav21ws-7-f d6 dl4936 d8 mbrs4201t3g d4 uf4002 vr1 p6ke200a r20 10 k br1 2kbp06m 600 v f1 3.15 a rv1 275 vac c8 330 f 50 v c7 2.2 nf 250 vac c10 330 f 50 v c4 10 f 16 v c12 1 f 50 v c13 100 nf 50 v c5 22 f 50 v linkswitch-ph u1 lnk406eg c3 1 f 400 v c1 47 nf 275 vac c2 100 nf 630 v r18 510 1 w c11 220 nf 630 v r12 15 1% r13 130 1/2 w d1 dl4002 q2 irfr310 vr2 zmm5245b-7 15 v q1 fmmt558 c6 15 nf 50 v figure 7. schematic of an isolated, triac dimmable, high power factor, universal input, 14 w led driver.
rev. d 08/11 6 lnk403-409/413-419 www.powerint.com diode d3 and vr1 clamp the drain voltage to a safe level due to the effects of leakage inductance. diode d4 is necessary to prevent reverse current from fowing through u1 for the period of the rectifed ac input voltage that the voltage across c2 falls to below the refected output voltage (v or ). diode d6, c5, r7 and r8 create the primary bias supply from an auxiliary winding on the transformer. capacitor c4 provides local decoupling for the bypass pin of u1 which is the supply pin for the internal controller. during start-up c4 is charged to ~6 v from an internal high-voltage current source tied to the device drain pin. this allows the part to start switching at which point the operating supply current is provided from the bias supply via r5. capacitor c4 also selects the output power mode (10 m f for reduced power was selected to reduce dissipation in u1 and increase effciency). feedback the bias winding voltage is proportional to the output voltage (set by the turns ratio between the bias and secondary windings). this allows the output voltage to be monitored without secondary side feedback components. resistor r6 converts the bias voltage into a current which is fed into the feedback pin of u1. the internal engine within u1 combines the feedback pin current, voltage monitor pin current and drain current information to provide a constant output current over a 1.5:1 output voltage variation (led string voltage variation of 25%) at a fxed line input voltage. to limit the output voltage at no-load an output overvoltage protection circuit is set by d7, c12, r20, vr3, c13, q3 and r19. should the output load be disconnected then the bias voltage will increase until vr3 conducts, turning on q3 and reducing the current into the feedback pin. when this current drops below 20 m a the part enters auto-restart and switching is disabled for 1500 ms allowing time for the output and bias voltages to fall. output rectifcation the transformer secondary winding is rectifed by d8 and fltered by c8 and c10. a schottky barrier diode was selected for effciency and the combined value of c8 and c10 were selected to give peak-to-peak and led ripple current equal to 40% of the mean value. for designs where lower ripple is desirable the output capacitance value can be increased. a small pre-load is provided by r15 which limits the output voltage under no-load conditions. triac phase dimming control compatibility the requirement to provide output dimming with low cost, triac-based, leading edge phase dimmers introduces a number of trade-offs in the design. due to the much lower power consumed by led based lighting the current drawn by the overall lamp is below the holding current of the triac within the dimmer. this can cause undesirable behaviors such as limited dimming range and/or fickering as the triac fres inconsistently. the relatively large impedance the led lamp presents to the line allows signifcant ringing to occur due to the inrush current charging the input capacitance when the triac turns on. this too can cause similar undesirable behavior as the ringing may cause the triac current to fall to zero and turn off. to overcome these issues two circuits, the active damper and passive bleeder, are incorporated. the drawback of these circuits is increased dissipation and therefore reduced effciency of the supply. for non-dimming applications these components can simply be omitted. the active damper consists of components r9, r10, r11, r12, d1, q1, c6, vr2, q2 in conjunction with r13. this circuit limits the inrush current that fows to charge c2 when the triac turns on by placing r13 in series for the frst 1 ms of the triac conduction. after approximately 1 ms, q2 turns on and shorts r13. this keeps the power dissipation on r13 low and allows a larger value during current limiting. resistor r9, r10, r11 and c6 provide the 1 ms delay after the triac conducts. transistor q1 discharges c6 when the triac is not conducting and vr2 clamps the gate voltage of q2 to 15 v. the passive bleeder circuit is comprised of c11 and r18. this helps to keep the input current above the triac holding current while the input current corresponding to the effective driver resistance increases during each ac half-cycle.
rev. d 08/11 7 lnk403-409/413-419 www.powerint.com 7 w high power factor non-dimmable led driver design example with enhanced line regulation the circuit schematic in figure 7 shows a high power-factor led driver based on a LNK413EG from the linkswitch-ph family of devices. it was optimized to drive an led string at a voltage of 21 v with a constant current of 0.33 a, ideal for par20/par30 lamp retro-ft applications. the design operates over the universal input voltage range of 90 vac to 265 vac and is a non-dimming application. a non-dimming application has tighter output current variation with changes in the line voltage than a dimming application. its key to note that, although not specifed for dimming, no circuit damage will result if the end user does operate the design with a phase controlled dimmer. circuit description input stage fuse f1 provides protection from component failures while rv1 provides a clamp during differential line surges, keeping the peak drain voltage of u1 below the 725 v rating of the internal power fet. bridge rectifer br1 rectifes the ac line voltage. emi fltering is provided by l1-l3, c2 together with the safety rated y class capacitor (c7) that bridges the safety isolation barrier between primary and secondary. resistor r2 and r3 act to damp any resonances formed between l1, l2, c2 and the ac line impedance. a small bulk capacitor (c3) is required to provide a low impedance source for the primary switching current. the maximum value of c2 and c3 is limited in order to maintain a power factor of greater than 0.9. linkswitch-ph primary to provide peak line voltage information to u1 the incoming rectifed ac peak charges c8 via d6. this is then fed into the voltage monitor pin of u1 as a current via r4, r7 and r8. the voltage monitor pin current and the feedback pin current are used internally to control the average output led current. the combined value of r4, r7 and r8 (3.909 m w ) and r11, r12 (1.402 m w ) connected to the voltage monitor pin provides excellent line regulation over the entire 90 vac to 265 vac input range. the voltage monitor pin current is also used by the device to set the line input overvoltage and undervoltage protection thresholds. diode d1 and vr1 clamp the drain voltage to a safe level due to the effects of leakage inductance. a zener clamp was selected for lowest component count and highest effciency. diode d5 is necessary to prevent reverse current from fowing through u1 during the period when the ac input voltage is lower than the refected output voltage (v or ). a space effcient rm6 core was selected for this design. the rm core geometry helps minimizes audible noise but requires the use of fying leads to meet safety spacing requirements. diode d3, c6, r5, r9 and r18 create the primary bias supply from an auxiliary winding on the transformer. resistor r5 provides fltering of leakage inductance generated voltage spikes to improve tracking of the bias and output voltages. it also forms a pole with c6 at ~100 hz. resistors r9 and r18 act as a small load to ensure that the bias voltage collapses during output short-circuit when u1 enters auto-restart operation to protect the supply. output overvoltage and load disconnection protection is provided by d8, c14, r24, vr3, c15, r23 and q2. should the output led load become disconnected the output voltage will rise causing an associated rise in the bias winding voltage across c14. once this exceeds the voltage rating of vr3, q2 turns on pulling down the feedback pin of u1 and initiating auto-restart operation. once in auto-restart the low duty cycle of operation (~3%) together with the small pre-load on the output prevents the output voltage rising to a high level. once the output load is reconnected normal operation resumes. capacitor c12 provides local decoupling for the bypass pin of u1 which is the supply pin for the internal controller. during figure 8. schematic of an isolated, non-dimmable, high power factor, universal input, 7 w led driver. pi-5991-101210 d s bp v r fb control fl2 t1 rm6 fl1 1 fl3 6 2 r4 2 m 1% r2 1 k l1 1000 h l3 1000 h l2 1000 h r3 1 k r7 1 m 1% r8 909 k 1% r11 1.0 m 1% r12 402 k 1% r19 24.9 k 1% r15 150 k r6 20 k 21 v, 330 ma 90 - 265 vac rtn l n r9 10 k r18 10 k r5 75 r10 3 k r23 1 k d6 dl4007 d1 uf4007 d4 1n4148 vr3 zmm5259b-7 39 v q2 mmbt3904 d8 bav21ws-7-f d3 dl4936 d2 mbrs4201t3g d5 es1d vr1 p6ke200a r24 10 k br1 df06s-e3/45 600 v f1 3.15 a rv1 275 vac c5 150 f 35 v c7 2.2 nf 250 vac c4 150 f 35 v c12 10 f 10 v c14 1 f 50 v c15 100 nf 50 v c6 22 f 50 v linkswitch-ph u1 LNK413EG c8 1 f 400 v c2 22 nf 275 vac c3 100 nf 400 v
rev. d 08/11 8 lnk403-409/413-419 www.powerint.com start-up c4 is charged to ~6 v from an internal high-voltage current source tied to the device drain pin. once the bias voltage has risen into regulation the operating supply current is provided via r10. diode d4 prevents u1 from charging c6 during start-up which would increase the start-up delay time. feedback the bias winding voltage is proportional to the output voltage (set by the turns ratio between the bias and secondary windings). this allows the output voltage to be monitored without secondary side feedback components. resistor r15 converts the bias voltage into a current which is fed into the feedback pin of u1. the internal engine within u1 combines the feedback pin current, voltage monitor pin current and drain current information to provide a constant output current over a 2:1 output voltage range. output rectifcation the transformer secondary winding is rectifed by d2 and fltered by c4 and c5. a schottky barrier diode was selected for effciency and the combined value of c4 and c5 were selected to give an acceptable led ripple current. for designs where lower ripple is desirable the output capacitance value can be increased. a small pre-load is provided by r6 which limits the output voltage under no-load conditions. key application considerations power table the data sheet power table (table 1) represents the minimum and maximum practical continuous output power based on the following conditions: 1. effciency of 80% 2. device local ambient of 70 c 3. suffcient heat sinking to keep the device temperature below 100 c 4. for minimum output power column ? refected output voltage (v or ) of 120 v ? feedback pin current of 135 m a ? bypass pin capacitor value of 10 m f 5. for maximum output power column ? refected output voltage (v or ) of 65 v ? feedback pin current of 165 m a ? bypass pin capacitor value of 100 m f (lnk4x3eg = 10 m f) note that input line voltages above 85 vac do not change the power delivery capability of linkswitch-ph devices. device selection select the device size by comparing the required output power to the values in table 1. for thermally challenging designs, e.g. incandescent lamp replacement, where either the ambient temperature local to the linkswitch-ph device is high and/or there is minimal space for heat sinking use the minimum output power column. this is selected by using a 10 m f bypass pin capacitor and results in a lower device current limit and therefore lower conduction losses. for open frame design or designs where space is available for heat sinking then refer to the maximum output power column. this is selected by using a 100 m f bypass pin capacitor for all but the lnk4x3 which has only one power setting. in all cases in order to obtain the best output current tolerance maintain the device temperature below 100 c maximum input capacitance to achieve high power factor, the capacitance used in both the emi flter and for decoupling the rectifed ac (bulk capacitor) must be limited in value. the maximum value is a function of the output power of the design and reduces as the output power reduces. for the majority of designs limit the total capacitance to less than 200 nf with a bulk capacitor value of 100 nf. film capacitors are recommended compared to ceramic types as they minimize audible noise with operating with leading edge phase dimmers. start with a value of 10 nf for the capacitance in the emi flter and increase in value until there is suffcient emi margin. reference pin resistance value selection the linkswitch-ph family contains phase dimming devices, lnk403-409, and non-dimming devices, lnk413-419. the non-dimmable devices use a 24.9 k w 1% reference pin resistor in high-line and universal input voltage designs and 49.9 k w 1% in low-line input voltage designs, for best output current tolerance (over ac input voltage changes). the dimmable devices use 49.9 k w 1% to achieve the widest dimming range. voltage monitor pin resistance network selection for widest ac phase angle dimming range with lnk403-409, use a 4 m w resistor connected to the line voltage peak detector circuit. make sure that the resistors voltage rating is suffcient for the peak line voltage. if necessary use multiple series connected resistors. for best line regulation, use a series combination of resistors that equals 3.909 m w connected to the line voltage peak detector. in addition, connect a 1 m w in series with a 402 k w resistor (1.402 m w total) from the voltage monitor pin to source pin. use 1% tolerance resistors for good accuracy. line regulation can be further improved by using the pixls spreadsheets fne tuning section. see the linkswitch-ph application note for more information. primary clamp and output refected voltage v or a primary clamp is necessary to limit the peak drain to source voltage. a zener clamp requires the fewest components and board space and gives the highest effciency. rcd clamps are also acceptable however the peak drain voltage should be carefully verifed during start-up and output short-circuit as the clamping voltage varies with signifcantly with the peak drain current. for the highest effciency, the clamping voltage should be selected to be at least 1.5 times the output refected voltage, v or , as this keeps the leakage spike conduction time short. when using a zener clamp in a universal input or high-line only application, a v or of less than 135 v is recommended to allow for the absolute tolerances and temperature variations of the zener. this will ensure effcient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the fet. an rcd (or rcdz) clamp
rev. d 08/11 9 lnk403-409/413-419 www.powerint.com provides tighter clamp voltage tolerance than a zener clamp. the rcd clamp is more cost effective than the zener clamp but requires more careful design to ensure that the maximum drain voltage does not exceed the power fet breakdown voltage. these v or limits are based on the bv dss rating of the internal fet, a v or of 60 v to 100 v is typical for most designs, giving the best pfc and regulation performance. series drain diode an ultra-fast or schottky diode in series with the drain is necessary to prevent reverse current fowing through the device. the voltage rating must exceed the output refected voltage, v or . the current rating should exceed two times the average primary current and have a peak rating equal to the maximum drain current of the selected linkswitch-ph device. line voltage peak detector circuit linkswitch-ph devices use the peak line voltage to regulate the power delivery to the output. a capacitor value of 1 m f to 4.7 m f is recommended to minimize line ripple and give the highest power factor (>0.9), smaller values are acceptable but result in lower pf and higher line current distortion. operation with phase controlled dimmers dimmer switches control incandescent lamp brightness by not conducting (blanking) for a portion of the ac voltage sine wave. this reduces the rms voltage applied to the lamp thus reducing the brightness. this is called natural dimming and the linkswitch-ph lnk403-409 devices when confgured for dimming utilize natural dimming by reducing the led current as the rms line voltage decreases. by this nature, line regulation performance is purposely decreased to increase the dimming range and more closely mimic the operation of an incandescent lamp. using a 49.9 k w reference pin resistance selects natural dimming mode operation. leading edge phase controlled dimmers the requirement to provide ficker-free output dimming with low cost, triac-based, leading edge phase dimmers introduces a number of trade-offs in the design. due to the much lower power consumed by led based lighting the current drawn by the overall lamp is below the holding current of the triac within the dimmer. this causes undesirable behaviors such as limited dimming range and/or fickering. the relatively large impedance the led lamp presents to the line allows signifcant ringing to occur due to the inrush current charging the input capacitance when the triac turns on. this too can cause similar undesirable behavior as the ringing may cause the triac current to fall to zero and turn off. to overcome these issues two circuits, the active damper and passive bleeder, are incorporated. the drawback of these circuits is increased dissipation and therefore reduced effciency of the supply so for non-dimming applications these components can simply be omitted. figure 9(a) shows the line voltage and current at the input of a leading edge triac dimmer with figure 9(b) showing the resultant rectifed bus voltage. in this example, the triac conducts at 90 degrees. figure 10 shows undesired rectifed bus voltage and current with the triac turning off prematurely and restarting. if the triac is turning off before the end of the half-cycle erratically or alternate half ac cycles have different conduction angles then ficker will be observed in the led light due to variations in the output current. this can be solved by including a bleeder and damper circuit. dimmers will behave differently based on manufacturer and power rating, for example a 300 w dimmer requires less dampening and requires less power loss in the bleeder than a 600 w or 1000 w dimmer due to different drive circuits and triac holding current specifcations. line voltage also has a signifcant impact as at high-line for a given output power the input current and therefore triac current is lower but the peak inrush current when the input capacitance charges is higher creating more ringing. finally multiple lamps in parallel driven from the same dimmer can introduce more ringing due to the increased capacitance of parallel units. therefore when testing dimmer operation verify on a number of models, different line voltages and with both a single driver and multiple drivers in parallel. 50 100 150 200 250 300 350 400 conduction angle () line voltage (at dimmer input) (v) line current (through dimmer) (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5983-060810 voltage current 0.5 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5984-060810 voltage current figure 9. (a) ideal input voltage and current waveforms for a leading edge triac dimmer at 90 conduction angle. (b) resultant waveforms following rectication of triac dimmer output.
rev. d 08/11 10 lnk403-409/413-419 www.powerint.com start by adding a bleeder circuit. add a 0.44 m f capacitor and 510 w 1 w resistor (components in series) across the rectifed bus (c11 and r18 in figure 7). if this results in satisfactory operation reduce the capacitor value to the smallest that results in acceptable performance to reduce losses and increase effciency. if the bleeder circuit does not maintain conduction in the triac, then add an active damper as shown in figure 7. this consists of components r9, r10, r11, r12, d1, q1, c6, vr2, q2 in conjunction with r13. this circuit limits the inrush current that fows to charge c2 when the triac turns on by placing r13 in series for the frst 1 ms of the triac conduction. after approximately 1 ms, q2 turns on and shorts r13. this keeps the power dissipation on r13 low and allows a larger value to be used during current limiting. increasing the delay before q2 turns on by increasing the values of resistors r9 and r10 will improve dimmer compatibility but cause more power to be dissipated across r13. monitor the ac line current and voltage at the input of the power supply as you make the adjustments. increase the delay until the triac operates properly but keep the delay as short as possible for effciency. as a general rule the greater the power dissipated in the bleeder and damper circuits, the more dimmer types will work with the driver. trailing edge phase controlled dimmers figure 11 shows the line voltage and current at the input of the power supply with a trailing edge dimmer. in this example, the dimmer conducts at 90 degrees. many of these dimmers use back-to-back connected power fets rather than a triac to control the load. this eliminates the holding current issue of triacs and since the conduction begins at the zero crossing, high current surges and line ringing are minimized. typically these types of dimmers do not require damping and bleeder circuits. audible noise considerations for use with leading edge dimmers noise created when dimming is typically created by the input capacitors, emi flter inductors and the transformer. the input capacitors and inductors experience high di/dt and dv/dt every ac half-cycle as the triac fres and an inrush current fows to charge the input capacitance. noise can be minimized by selecting flm vs ceramic capacitors, minimizing the capacitor value and selecting inductors that are physically short and wide. the transformer may also create noise which can be minimized by avoiding cores with long narrow legs (high mechanical resonant frequency). for example, rm cores produce less audible noise than ee cores for the same fux density. reducing the core fux density will also reduce the noise. reducing the maximum fux density (bm) to 1500 gauss usually eliminates any audible noise but must be balanced with the increased core size needed for a given output power. thermal and lifetime considerations lighting applications present thermal challenges to the driver. in many cases the led load dissipation determines the working ambient temperature experienced by the drive so thermal evaluation should be performed with the driver inside the fnal enclosure. temperature has a direct impact on driver and led lifetime. for every 10 c rise in temperature, component life is reduced by a factor of 2. therefore it is important to properly heat sink and verify the operating temperatures of all devices. 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5985-102810 voltage current figure 10. example of phase angle dimmer showing erratic firing. 50 100 150 200 250 300 350 conduction angle () dimmer output voltage (v) dimmer output current (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5986-060810 voltage current 0 figure 11. ideal dimmer output voltage and current waveforms for a trailing edge dimmer at 90 conduction angle.
rev. d 08/11 11 lnk403-409/413-419 www.powerint.com layout considerations primary side connections use a single point (kelvin) connection at the negative terminal of the input flter capacitor for the source pin and bias returns. this improves surge capabilities by returning surge currents from the bias winding directly to the input flter capacitor. the bypass pin capacitor should be located as close to the bypass pin and connected as close to the source pin as possible. the source pin trace should not be shared with the main power fet switching currents. all feedback pin figure 12. rd-193 7 w layout example, top layer. components that connect to the source pin should follow the same rules as the bypass pin capacitor. it is critical that the main power fet switching currents return to the bulk capacitor with the shortest path as possible. long high current paths create excessive conducted and radiated noise. secondary side connections the output rectifer and output flter capacitor should be as close as possible. the transformers output return pin should have a short trace to the return side of the output flter capacitor. pi-5987-060110 f1 rv1 l1 c2 r3 r16 r2 l3 c9 r14 c3 vr1 d1 c8 u1 fl1 t1 5 6 1 2 3 4 c7 transformer c12 c5 c4 v v c6 r10 d8 vr3 r24 c14 c15 r15 fl2 fl3 r23 l2 l n output filter capacitors bypass pin capacitor copper area for heat sinking input emi filter bulk capacitor lnk403eg clamp
rev. d 08/11 12 lnk403-409/413-419 www.powerint.com figure 13. rd-193 7 w layout example, bottom layer. pi-5988-060110 vr2 r4 r7 r20 c13 br1 s s d7 r17 d1 r13 d6 r12 d1 d5 r9 d3 r5 r19 d2 r6 r18 f1 b3 output rectifier bridge rectifier active damper mosfet quick design checklist maximum drain voltage verify that the peak v ds does not exceed 725 v under all operating conditions including start up and fault conditions. maximum drain current measure the peak drain current under all operation conditions including start up and fault conditions. look for signs of transformer saturation (usually occurs at highest operating ambient temperatures). verify that the peak current is less that stated for the absolute maximum rating in the data sheet. thermal check at maximum output power, both minimum and maximum line voltage and ambient temperature; verify that temperature specifcations are not exceeded for the linkswitch-ph, transformer, output diodes, output capacitors and drain clamp components.
rev. d 08/11 13 lnk403-409/413-419 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units control functions switching frequency f osc t j = 25 c average 62 66 70 khz peak-peak jitter 9 frequency jitter modulation rate f m t j = 25 c see note b 1 khz bypass pin charge current i ch1 v bp = 0 v, t j = 25 c lnk403 , lnk413 -5.0 -4.2 -3.4 ma lnk404 , lnk414 -9.6 -8.0 -6.4 lnk405-409 , lnk415-419 -15 -11.9 -8.8 i ch2 v bp = 5 v, t j = 25 c lnk403 , lnk413 -1.6 -1.2 -0.6 lnk404 , lnk414 -4.2 -3.5 -2.8 lnk405-409 , lnk415-419 -8.2 -6.4 -4.6 charging current temperature drift see note a 0.5 %/c bypass pin voltage v bp 0 c < t j < 100 c 5.7 5.9 6.1 v bypass pin voltage hysteresis v bp(h) 0 c < t j < 100 c 0.85 v bypass pin shunt voltage v bp(shunt) i bp = 2 ma 0 c < t j < 100 c 6.0 6.4 6.7 v soft-start time t soft t j = 25 c v bp = 5.9 v 40 ms absolute maximum ratings (1,4) drain pin peak current (5) : lnk403, lnk413 ................... 1.37 a lnk404, lnk414 ................... 2.08 a lnk405, lnk415 ................... 2.72 a lnk406, lnk416 .................. 4.08 a lnk407, lnk417 .................. 5.44 a lnk408, lnk418 .................. 6.88 a lnk409, lnk419 ................... 7.73 a drain pin voltage ................ -0.3 to 725 v bypass pin voltage ................. -0.3 to 9 v bypass pin current ..................... 100 ma voltage monitor pin voltage ....................-0.3 to 9 v feedback pin voltage .. .................................. -0.3 to 9 v reference pin voltage .......................................... -0.3 to 9 v lead temperature (3) ....................................................... ......... 260 c storage temperature . .................. -65 to 150 c operating junction temperature (2) ......................... -40 to 150 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. absolute maximum ratings specifed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. 5. peak drain current is allowed while the drain voltage is simultaneously less than 400 v. see also figure 17. thermal resistance thermal resistance: esip package: ( q ja ) .......................... .......................... 105 c/w (1) ( q jc ) ............................................... ........... 2 c/w (2) notes: 1. free standing with no heat sink. 2. measured at back surface tab.
rev. d 08/11 14 lnk403-409/413-419 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units control functions (cont.) drain supply current i cd2 0 c < t j < 100 c fet not switching 1.0 1.3 1.6 ma i cd1 0 c < t j < 100 c fet switching at f osc 0.9 1.5 2.25 voltage monitor pin line brown-in threshold current i uv+ t j = 25 c r r = 24.9 k w 21.0 22.5 24.0 m a r r = 49.9 k w 22.8 24.5 26.2 line brown-out threshold current i uv- t j = 25 c r r = 24.9 k w 18.5 m a r r = 49.9 k w 15.0 line brown-in/out hysteresis i uv(h) t j = 25 c r r = 24.9 k w 1 4 m a r r = 49.9 k w 5 9.4 line overvoltage threshold i ov t j = 25 c r r = 24.9 k w r r = 49.9 k w threshold 107 112 117 m a hysteresis 4 voltage monitor pin voltage v v 0 c < t j < 100 c i uv- < i v < i ov 2.75 3.0 3.25 v voltage monitor pin short-circuit current i v(sc) v v = 5 v t j = 25 c 170 190 210 m a remote on/off threshold v v(rem) t j = 25 c 0.5 v feedback pin feedback pin current at onset of maximum duty cycle i fb(dcmaxr) 0 c < t j < 100 c 85 m a feedback pin current skip cycle threshold i fb(skip) 0 c < t j < 100 c 220 m a maximum duty cycle dc max i fb(dcmaxr) < i fb < i fb(skip) 0 c < t j < 100 c 90 99.9 % feedback pin voltage v fb i fb = 150 m a 0 c < t j < 100 c 2.08 2.40 2.62 v feedback pin short-circuit current i fb(sc) v fb = 5 v t j = 25 c 320 400 480 m a duty cycle reduction dc10 i fb = i fb(ar) , t j = 25 c, see note b 10 % dc40 i fb = 40 m a, t j = 25 c 20 dc60 i fb = 60 m a, t j = 25 c 36
rev. d 08/11 15 lnk403-409/413-419 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units auto-restart auto-restart on-time t ar t j = 25 c v bp = 5.9 v 40 ms auto-restart duty cycle dc ar t j = 25 c 3.1 % soa minimum switch on-time t on(soa) t j = 25 c see note b 1.75 m s feedback pin current during auto-restart i fb(ar) 0 c < t j < 100 c 17.5 m a reference pin reference pin voltage v r r r = 24.9 k w 0 c < t j < 100 c 1.215 1.245 1.275 v reference pin current i r 48.45 49.70 50.95 m a current limit/circuit protection full power current limit (c bp = 100 m f) i limit(f) t j = 25 c di/dt = 174 ma/ m s lnk404, lnk414 1.02 1.18 a di/dt = 174 ma/ m s lnk405, lnk415 1.24 1.44 di/dt = 225 ma/ m s lnk406, lnk416 1.50 1.74 di/dt = 320 ma/ m s lnk407, lnk417 1.77 2.06 di/dt = 350 ma/ m s lnk408, lnk418 2.39 2.77 di/dt = 426 ma/ m s lnk409, lnk419 3.26 3.79 reduced power current limit ( c bp = 10 m f) i limit(r) t j = 25 c di/dt = 133 ma/ m s lnk403, lnk413 0.75 0.85 a di/dt = 195 ma/ m s lnk404, lnk414 0.81 0.94 di/dt = 192 ma/ m s lnk405, lnk415 1.00 1.16 di/dt = 240 ma/ m s lnk406, lnk416 1.19 1.38 di/dt = 335 ma/ m s lnk407, lnk417 1.42 1.66 di/dt = 380 ma/ m s lnk408, lnk418 1.73 2.01 di/dt = 466 ma/ m s lnk409 , lnk419 2.35 2.73 minimum on-time pulse t leb + t il(d) t j = 25 c 300 500 700 ns leading edge blanking time t leb t j = 25 c see note b 150 500 ns current limit delay t il(d) t j = 25 c see note b 150 ns thermal shutdown temperature 135 142 150 c thermal shutdown hysteresis 75 c bypass pin power-up reset threshold voltage v bp(reset) 0 c < t j < 100 c 2.25 3.5 4.25 v
rev. d 08/11 16 lnk403-409/413-419 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units output on-state resistance r ds(on) lnk403, lnk413 i d = 100 ma t j = 25 c 9.00 10.35 w t j = 100 c 13.50 15.5 lnk404, lnk414 i d = 100 ma t j = 25 c 5.40 6.25 t j = 100 c 8.35 9.7 lnk405, lnk415 i d = 150 ma t j = 25 c 4.10 4.7 t j = 100 c 6.30 7.3 lnk406, lnk416 i d = 150 ma t j = 25 c 2.80 3.2 t j = 100 c 4.10 4.75 lnk407, lnk417 i d = 200 ma t j = 25 c 2.00 2.3 t j = 100 c 3.10 3.6 lnk408, lnk418 i d = 250 ma t j = 25 c 1.60 1.85 t j = 100 c 2.40 2.8 lnk409, lnk419 i d = 350 ma t j = 25 c 1.40 1.6 t j = 100 c 2.1 2.45 off-state drain leakage current i dss v bp = 6.4 v v ds = 560 v t j = 100 c 50 m a breakdown voltage bv dss v bp = 6.4 v t j = 25 c 725 v minimum drain supply voltage t j < 100 c 36 v rise time t r measured in a typical flyback 100 ns fall time t f 50 ns notes: a. for specifcations with negative values, a negative temperature coeffcient corresponds to an increase in magnitude with increas - ing temperature and a positive temperature coeffcient corresponds to a decrease in magnitude with increasing temperature. b. guaranteed by characterization. not tested in production.
rev. d 08/11 17 lnk403-409/413-419 www.powerint.com typical performance characteristics figure 14. drain capacitance vs. drain pin voltage. figure 15. power vs. drain voltage. figure 16. drain current vs. drain voltage. figure 17. maximum allowable drain current vs. drain voltage. 0 100 200 300 400 500 600 0 100 1000 10000 pi-5992-101110 drain pin voltage (v) drain capacitance (pf) lnk403, lnk413 0.18 lnk404, lnk414 0.28 lnk405, lnk415 0.38 lnk406, lnk416 0.56 lnk407, lnk417 0.75 lnk408, lnk418 1.00 lnk409, lnk419 1.16 scaling factors: 300 100 200 0 0 200 100 400 500 600 300 700 drain voltage (v) power (mw) pi-5993-101110 lnk403, lnk413 0.18 lnk404, lnk414 0.28 lnk405, lnk415 0.38 lnk406, lnk416 0.56 lnk407, lnk417 0.75 lnk408, lnk418 1.00 lnk409, lnk419 1.16 scaling factors: 0 0 2 4 6 8 10 12 14 16 18 20 drain voltage (v) drain current (a) pi-5994-101110 2 3 1 lnk408 t case = 25 c lnk408 t case = 100 c 4 5 lnk403, lnk413 0.18 lnk404, lnk414 0.28 lnk405, lnk415 0.38 lnk406, lnk416 0.56 lnk407, lnk417 0.75 lnk408, lnk418 1.00 lnk409, lnk419 1.16 scaling factors: 0 0 100 200 300 400 600 500 700 800 drain voltage (v) drain current (normalized to absolute maximum rating) pi-6010-060410 0.6 0.8 0.4 0.2 1 1.2
rev. d 08/11 18 lnk403-409/413-419 www.powerint.com pi-4917-061510 mounting hole pattern (not to scale) pin 7 pin 1 0.100 (2.54) 0.100 (2.54) 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93) 0.020 (0.50) notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) front view 2 2 b a 0.070 (1.78) ref. pin #1 i.d. 3 c 0.016 (0.41) ref. 0.290 (7.37) ref. 0.047 (1.19) 0.100 (2.54) 0.519 (13.18) ref. 0.198 (5.04) ref. 0.264 (6.70) ref. 0.118 (3.00) 6 6 3 0.140 (3.56) 0.120 (3.05) 0.021 (0.53) 0.019 (0.48) 0.378 (9.60) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 0.048 (1.22) 0.046 (1.17) 0.081 (2.06) 0.077 (1.96) 0.207 (5.26) 0.187 (4.75) 0.033 (0.84) 0.028 (0.71) 0.016 (0.41) 0.011 (0.28) esip-7c (e package) 10 ref. all around 0.020 m 0.51 m c 0.010 m 0.25 m c a b side view end view back view 4 0.023 (0.58) 0.027 (0.70) detail a detail a
rev. d 08/11 19 lnk403-409/413-419 www.powerint.com part ordering information ? linkswitch product family ? ph series number ? package identifer e esip-7c l esip-7f ? package material g green: halogen free and rohs compliant lnk 409 e g 1 7 end view 0.021 (0.53) 0.019 (0.48) 0.060 (1.52) ref. 0.019 (0.48) ref. 0.378 (9.60) ref. 0.048 (1.22) 0.046 (1.17) c side view 6 0.129 (3.28) 0.122 (3.08) 0.081 (2.06) 0.077 (1.96) detail a 0.084 (2.14) 0.047 (1.19) ref. 0.290 (7.37) ref. 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 pi-5204-061510 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). esip-7f (l package) 2 a b 1 7 bottom view pin 1 i.d. 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) 0.070 (1.78) ref. exposed pad hidden exposed pad up 2 1 7 top view 0.089 (2.26) 0.079 (2.01) 0.173 (4.40) 0.163 (4.15) 0.198 (5.04) ref. 0.264 (6.70) ref. 0.100 (2.54) 0.490 (12.45) ref. 6 0.033 (0.84) 0.028 (0.71) 0.010 m 0.25 m c a b 4 3 0.020 (0.50) 0.023 (0.58) 0.027 (0.70) detail a (not drawn to scale)
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2011, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a initial release. 06/09/10 b updated power table. 08/06/10 c added non-dimming parts and related text. 11/10 d added l package. 08/11

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